QSC Q-SYS PS-1650G Manual de usuario descargar pdf (Pagina 18)

by the Nios II processor code or JTAG interface, and also to the Nios II processor's reset input

interface. The cpu_subsystem cpu_reset interface connects to the Nios II processor's reset input

interface. The top_level.qsys file connects the cpu_jtag_debug_reset interface to the cpu_reset

interface.

9. Connect the memory_tester_subsystem write_master and read_master interfaces to either the

sdram s1 interface (for ALTMEMPHY-based designs), or sdram avl interface (for UniPHY-based

designs).

10.Connect the memory_tester_subsystem slave interface to the cpu_subsystem master interface.

11.Maintain the base addresses of 0x0 for the memory_tester_subsystem slave interface, and for either

the sdram s1 interface (for ALTMEMPHY-based designs), or sdram avl interface (for UniPHY-based

designs).

The two slave interfaces can use the same address map range because different masters control them. The

cpu_subsystem master interface controls the memory_tester_subsystem, and the

memory_tester_subsystem write_master and read_master interfaces control the sdram interface.

Viewing the Memory Tester System in Qsys

You can use the Hierarchy tab, accessed from the View menu, to show the complete hierarchy of your

design. The Hierarchy tab is a full system hierarchical navigator, which expands the system contents to

show modules, interfaces, signals, contents of subsystems, and connections. The graphical interface of the

Hierarchy tab displays a unique icon for each element represented in the system, including interfaces,

directional pins, IP blocks, and system icons that show exported interfaces and the instances of

components that make up a system.

Click Generate > HDL Example to view the HDL for an example instantiation of the system. The HDL

example lists the signals from the exported interfaces in the system. The signal names are the exported

interface name followed by an underscore, and then the signal name specified in the component or IP

core. Most of the signals connect to the external SDRAM device.

Compiling and Downloading Software to a Development Board

Before you begin

Altera recommends that you download the memory tester system to a development board to complete the

design process and test the memory interface of the board. If you do not have a development board you

can follow the steps provided in the accompanying readme.txt file to learn more details about porting

designs to FPGA devices or boards.

The Altera-provided software tests the memory using various test parameters and patterns, and is scripted

for compilation and download to the board.

1. To download the top-level system to a development board, in Qsys, click Generate > Generate.

2. Select the language for Create HDL design files for synthesis, and turn off the option to create a Block

Symbol File (.bsf).

3. Click Generate. Qsys generates HDL files for the system and the Quartus II IP File (.qip) that provides

the list of required HDL files for the Quartus II compilation.

4. When Qsys completes the generation, click Close.

Viewing the Memory Tester System in Qsys

TU-01006

2015.05.04

Altera Corporation

Qsys System Design Tutorial

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