QSC Q-SYS PS-1650G Manual de usuario descargar pdf (Pagina 17)

Verify the Memory Address Map

To ensure that the memory map of the system you create matches the memory map of other components,

you must verify the base addresses for the memory tester system. In Qsys, on the Address Map tab, verify

that the entries in Address Map table match the values in Table 3. Red exclamation marks indicate that

the address ranges overlap. Correct the base addresses, as appropriate, to ensure there are no overlapping

addresses.

Table 3: Address Map Table

Component Base Address Address

mm_bridge_0.s0 N/A N/A

pattern_generator_subsystem.slave 0x0 0x00000000 – 0x000007ff

pattern_checker_subsystem.slave 0x1000 0x0001000 – 0x000017ff

ram_test_controller.csr 0x800 0x00000800 – 0x0000081f

Save the System

At this point, there should be no remaining error messages in the Messages tab, and the system is

complete. Save the system.

Complete the Top-Level System

1. In Qsys, open the top_system.qsys file from the tt_qsys_design\quartus_ii_projects_for_boards\<develop‐

ment_board> directory.

The top-level system is set up for your development board, with an external clock source, a processor

system, and an SDRAM controller. You can view the clocks in top-level system on the Clock Settings

tab, and the partially-completed system connections on the System Contents tab.

2. In the IP Catalog, double-click memory_tester_system from the System group.

3. Click Finish to accept the default parameters, and to add the memory tester system to the top-level

system.

4. Rename the system to memory_tester_subsystem.

5. On the System Contents tab, use the arrows to move the memory_tester_subsystem up between the

cpu_subsystem and the sdram.

Since the cpu_subsystem controls the memory_tester_subsystem, and the

memory_tester_subsystem controls the sdram, this positioning allows you to more easily visualize

system performance.

6. Set the memory_tester_subsystem clk to either the sdram_sysclk (for ALTMEMPHY-based designs),

or sdram_afi_clk (for UniPHY-based designs).

Some boards have an FPGA and SDRAM device that use either the Altera DDR or DDR2 SDRAM

Controller with ALTMEMPHY; others use the Altera DDR3 SDRAM controller with UniPHY.

7. Connect the memory_tester_subsystem reset interface to the ext_clk clk_reset interface.

8. Connect the memory_tester_subsystem reset interface to the cpu_subsystem cpu_jtag_debug_reset

interface.

This design exports the Nios II processor JTAG debug reset output interface,

jtag_debug_module_reset, from the cpu_subsystem with the interface name cpu_ jtag_debug_reset.

The design must connect this Nios II reset output to any component reset inputs that require resetting

TU-01006

2015.05.04

Verify the Memory Address Map

Qsys System Design Tutorial

Altera Corporation

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